This invention relates to processes used to fabricate integrated circuits (ICs). More particularly, the present invention relates to a new and improved method of fabricating electrical connections and isolations between vertical circuit components, such as capacitor plates, and electrical conductors of interconnect layers of the IC, whereby the amount of space consumed by the connection or isolation is minimized, the number of process steps is minimized, and the process steps used are compatible with other process steps used to fabricate the IC.
Recent efforts in miniaturizing ICs have focused on reducing the space consumed by the circuit components. The ongoing evolution in miniaturizing IC components has resulted in reduced costs and more circuit functionality for a given substrate size and manufacturing cost. For example, only a few years ago spacing between adjoining circuit elements in a typical IC was in the neighborhood of two to three microns. Today, many ICs are being designed at spacing distances as small as 0.35 microns or less. To accommodate narrower spacing, the electrical conductors are reduced in width. The reduction in width is compensated for by increasing the thickness of the conductors to avoid degrading the quality of the signal conducted. Metal conductors have also been substituted for polysilicon conductors, because the metal conductors provide better signal conducting capabilities.
Increasing the thickness of the conductors also requires increases in the thickness of the dielectric insulation material which separates and covers the conductors and components. The thickness of the dielectric must be greater than the height or topology difference among the components, to provide adequate insulation to separate the layers and components of the IC structure from one another. Increases in the thickness of the dielectric material are possible, in part, as a result of advanced planarization techniques such as chemical mechanical polishing (CMP). CMP smooths relatively significant variations in the height of the different components to a planar surface. Smoothing the variable-height topology to a planar surface allows the typical lithographic semiconductor fabrication techniques to be used to form considerably more layers than were previously possible in IC construction. Previously, only one or two layers were typically constructed before the topology variations created such significant depth of focus problems with lithographic processes that any further precision fabrication of layered elements was prevented. However, because of CMP, the number of layers of the IC is no longer limited by the topology. Some present ICs are formed by as many as five or more separate metal or interconnect layers, each of which is separated by a CMP planarized dielectric layer. Consequently, CMP has created the opportunity to incorporate more circuitry on a single substrate in a single IC.
It is with regard to these and other considerations and problems that the present invention has evolved.
The improvements of the present invention relate to electrically connecting and electrically isolating vertically extending metal circuit components with respect to horizontally extending electrical conductors located above and below the circuit component in such a way that the resulting electrical connection or isolation does not consume an excessive amount of space, that a high quality electrical connection or isolation is established, and that there is no degradation in the electrical performance of the component. Another improvement involves fabricating the electrical connection or isolation in a multiple layer, metal interconnect IC, using fabrication methods which are similar to those used in forming the conductors of the interconnect layers and without revising the basic process steps involved in fabricating the interconnect layers. Another improvement involves fabricating the electrical connection or isolation without requiring any additional lithographic patterning steps or different materials from those which would otherwise be used in fabricating the interconnect layers.
In accordance with these and other improvements, the method of electrically connecting and isolating a vertically oriented metal element comprises the steps of connecting a lower end of the metal element to a conductor of a lower interconnect layer at a lower end of an opening in an inter-layer dielectric, extending an upper end of the metal element beyond an upper surface of the inter-layer dielectric, chemical mechanical polishing the extending upper end down flush with the upper surface of the inter-layer dielectric, covering the flush upper end with dielectric material, and positioning the upper interconnect layer over the dielectric material covering the flush upper end. The chemical mechanical polishing used to produce the flush upper end allows the dielectric material covering to effectively and precisely isolate the upper end of the metal element from vertically adjoining and horizontally extending conductors. The electrical isolation occurs in a vertical sense and therefore consumes very little space. Similarly, the lower end of the vertical metal element is connected to a horizontal conductor in a relatively small amount of space.
Other preferable aspects of the method involve chemical mechanical polishing of the surface of the dielectric material. The chemical mechanical polishing forms precise surfaces upon which lithographic patterning can be effectively performed. In addition, chemical vapor deposition or physical vapor deposition may be used to form the metal element, its lower end connection and the coating of dielectric material. Chemical vapor deposition allows the components to be formed in vertical orientations in vertical openings and allows metal elements to be formed conjunctively with the conductors of the interconnect layers, thereby simplifying the fabrication process. More than one metal element may be formed in the opening and positioned adjacent to the coating of dielectric material, all in a self-aligning manner which further simplifies the construction and does not require large spaces to accomplish. Only a minimum number of lithographic patterning steps are required when using the self-aligning aspects of the invention. The minimum use of lithographic patterning steps decreases the possibilities for error and simplifies the process.